The Data Plane is on Us




Have you tried the programmable NoC on AMD Versal™ adaptive SoCs? It connects the processing system, programmable logic, DDR memory, and other hard IP to significantly enhance data flow.

Available as hard IP across the entire Versal product portfolio, the Versal programmable NoC offers significant benefits over a soft IP implementation, including:

• Lower latency –
  Up to 58% lower latency versus the competition¹

• Faster development –
  Build time reductions of up to 50% versus competing FPGAs²

• Smaller design/device footprint –
  Logic utilization reductions of up to 60% versus the competition³


Why waste valuable programmable logic, engineering hours, power, and PCB real estate on baseline data plane infrastructure? With the Versal portfolio, you have the freedom to focus on differentiation and innovation.


Read White Paper
https://docs.amd.com/v/u/en-US/wp562-versal-noc